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Joined: 12/7/2011(UTC) Posts: 474 Location: Amsterdam
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Hi all, I'm looking for some extra explanation about the 4 Bit DPLL Bandwidth dip switch settings. The BIIISE has a nice description in the integration guide but that concerns a 3 bit setting. I have found the Github description which says: 4bit DPLL Bandwidth (switch 5 is the low bit) on = 0 off = 1 - 0b0000=default 0b0001=lowest 0b1111=highest Standard SW2 Dip sw 5-8 are ON = default. I interpreted the following: If switch 5 is the low bit than the setting 5= OFF, 6 = ON, 7 = ON, 8= ON will set the lowest value. Set all to OFF you will set the highest value. But how does it work with all the settings in between? Does someone has a matrix or logic for that? Many thanks! PS: the reason I have to play with this is that I bought an LG TV which I've connected via Toslink --> I2s. Due to some coincidence the LG and ESS make an unfortunate combination. Playing with the DPLL settings would provide the solution: see here
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