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Here is a scope shot of the noise that I am seeing on the LRCLK signal. It appears to be close to 80ns or 12Mhz which is the 8804 clock. Is this normal? Is there a way to clean it up a bit? sachsm attached the following image(s):  Noise.PNG (150kb) downloaded 57 time(s).You cannot view/download attachments. Try to login or register.
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I doubt it will cause any harm. I will see if I see the same thing.
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Did you get a chance to see what it looks like on your end? I am running my I2S lines to TTL inputs that have a Vil=.8V max,
these signal artifacts are greatly reducing my noise margin.
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Can you post a picture of your module layout? It seems like this would be related to contamination from wire routing.
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Yes, I think it is some sort of contamination from the coupling between devices. I have ~.5" of wire on the 3 I2S signals and 2" ground wire running between the SPDIF and the NI 7811R PXI device. The 7811R is a programmable FPGA device with TTL compatible inputs on SCSI-5 connectors. My goals is to use the FPGA to decode the I2S and provide a synchronous clock and start trigger to my other analog DAQ devices in the PXI chassis. It looks like I may need to optocouple the signals.... Edited by user Monday, April 2, 2012 12:12:12 PM(UTC)
| Reason: Not specified sachsm attached the following image(s): Setup.JPG (141kb) downloaded 34 time(s).You cannot view/download attachments. Try to login or register.
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