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Parallel lines on silk screen between QN2/3 and QN5/6 on Legato 2?
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NicMac  
#1 Posted : Saturday, January 29, 2011 1:25:57 PM(UTC)
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What do they mean? That thermal coupling between these pairs might reduce drift (or make them drift together)?
There is a similar thick line between QN2/3 on Ventus. Same story?
Just curios,
Nic
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avr300  
#2 Posted : Saturday, January 29, 2011 1:54:55 PM(UTC)
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Nic, do you mean lines like these (taken from Legato 1 silk screen)?

If so, they are just the flat side of the housing.

Edited by user Saturday, January 29, 2011 1:55:48 PM(UTC)  | Reason: Not specified

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NicMac  
#3 Posted : Saturday, January 29, 2011 1:59:25 PM(UTC)
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Yes - but on the Legato 2 board. They cannot indicate where to cut a trace as they are un top of, and parallel with, a traceThink
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avr300  
#4 Posted : Saturday, January 29, 2011 2:06:38 PM(UTC)
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No no, they doesn't indicate any cut.

They are simply indicating two flat sides (of two fet's or transistors), arranged in parallel. It's just the flat side of the fet. The lines should have been connected to the arches, to represent a TO92 case seen from the top. Do you see it ?

Edited by user Saturday, January 29, 2011 2:07:22 PM(UTC)  | Reason: Not specified
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NicMac  
#5 Posted : Saturday, January 29, 2011 2:27:35 PM(UTC)
NicMac

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You are right and I see it. The TPA silkscreens are very self-explanatory to avoid mistakes (just like the component labeling).
The parallel lines occur (and are visually striking) when the transistors are "face-to-face".
I have seen that sometimes transistors/fets are thermally coupled to make the "co-drift" and as I think a reduced drift was a major reason for the re-layout of the Ventus.
However, probably just a graphical thing as you point out.
Thanks,
Nic

Edited by user Saturday, January 29, 2011 2:54:53 PM(UTC)  | Reason: Not specified
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Russ White  
#6 Posted : Saturday, January 29, 2011 9:48:12 PM(UTC)
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I intentionally put those transistors face to face so that they could be glued or bound together with heat shrink tubing for thermal coupling. This reduces offset that might otherwise occur with changes in temperature.

I generally use a dab of thick orderless CA or 5 minute epoxy on one face and bond the transistors prior to soldering them in.

In practice, it is not at all necessary, just one more thing you can do if you like.

Edited by user Saturday, January 29, 2011 9:54:32 PM(UTC)  | Reason: Not specified
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