Brian Donegan wrote:Master clock != Bit Clock
Well, without beeing an expert, I tend to disagree on this one.Usually, the master clock has an higher rate than the bit clock.
Actually, another guy from diyaudio (NeoY2ks )that has build also a DAC around the ESS sabre 9018 told me this DAC does'nt need a SCLK to work but just the SDATA and LRClock lines....
So may be I gave a wrong assomption here, but could you develop on that?
Thx,
Arnaud
edit: here is what I found on the net :
«The new ESS Sabre DAC seems to use a novel approach. This is a DAC which
runs on its own clock (low jitter) and it accepts digital audio data in
SPDIF or I2S with an asynchronous clock (high jitter).
It is a multibit sigma-delta DAC so the input is highly oversampled
(don't remember how much) using polyphase filters, then the asynchronous
resampling is done on the highly oversampled data which allows use of a
very simple interpolation algorithm.
This is very clever (and patented).
It is a good example of lateral thought. Instead of solving a hard
problem (asynchronous resampling at frequencies close to the Nyquist
limit) it turns it into an easy problem (asynchronous resampling with a
sample frequency way above the Nyquist limit).
The chip incorporates lots of other extremely clever tricks.
It has been reported as potentially the best sounding chip ever by most
of those who tried to implement it.»
Edited by user Wednesday, July 15, 2009 12:18:45 PM(UTC)
| Reason: Not specified