Since I don't want to intrude to much on http://www.twistedpearau...t.aspx?g=posts&t=799 I'll just start my own topic :)

I'm going to use the Buffalo 32S in my pre-amp project. For this, I'm not going to be pleased with just one SPDIF input, specially sine I also have a SACD player.

So I want at least two SPDIF inputs (better three, including one optical), but also a I2S and DSD input to connect my SACD player.

the last two I want to do using two CAT5 cables and using balanced signal transmission using the four wire pairs:

DSD:
1. GND/Active
2. CLK
3. DSDL
4. DSDR

I2S:
1. GND/Active
2. CLK
3. LR CLK
4. DATA

For data transmission I might use two LTC1518/LTC1688 pairs. Obviously, I only need three pairs, sine one of them is just ground. The other wire of the ground pair will be used to indicate that there is an active signal on the wires.

My idea is to create some kind of logic to be able to switch the two signals to the Buffalo, probably via some AND ports and a simple pin to switch from DSD to I2C and back.

Then I need to switch between SPDIF and DSD/I2C. This probably needs to be done in two placed:
- first use a relay to switch the SPDIF header on and off
- make sure none of the other (DSD/I2C) data lines are active. This can probably be done via some simple logic circuitry.

And as for SPDIF switching: it's probably best to do that with some relays.

Anyway, that's it for the pre-amp part

The CD player is another matter. SPDIF is no problem, since that is already there, DSD an I2S are more difficult, these needs to be picked up via de DAC pins. The DAC used is a BB PCM1738. And as with the Buffalo, it has double meanings for the pins, but they are not compatible. So I will need to make some logic to automatically switch the signals (I hate manual stuff )

In case of the PCM1738, two pins are connected to GND in DSD mode, which are used as clock signals in I2S mode. So I came up with some simple circuit to detect the clocks. It comprises of a counter that is reset as long as there is a clock signal. If the signals are pulled to GND, the counter starts counting (clocked by an extra clock, can be fairly slow). When the counter is at it's highest state, it will stop, and a few loc AND's will result in a high signal indicating DSD mode. As soon as there is a clock applied at the input (I2S mode) the output will be low, indicating I2S mode). With this and some extra logic I can separate the two signals. I tested this with a simple simulation in multisim, and it looks like this might just work:



U3C is the output of the detector, and V2 is the clock input, using switch to simulate GDN/Clock states. This can probably be done easier, but it's a start. Ideas are welcome!

So, my real question is: can this me done... will this work?