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aolsen  
#1 Posted : Tuesday, June 30, 2009 3:40:52 PM(UTC)
aolsen

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Hi,

I am very interested in a combination of products to make a reference DAC:

- S/PDIF 4:1 MUX/Receiver Module
- Metronome ASRC Module
- Opus Dual-Mono DAC
- Volumite

The output will then be connected to a reference ClassD poweramplifer with balanced input.

My concern is how a can a reference clock be connected to these 3 parts and what should be the frequency?
When Volumite is connected the Opus are in SW mode - how can the digital filter be set then?

Thanks and best regards,

Allan
glt  
#2 Posted : Tuesday, June 30, 2009 9:39:41 PM(UTC)
glt

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Only Metronome needs a "reference clock" but it already has one. Since Metro is a asynchronous sample converter, it does not need the signal from the receiver and as a master it sends the clock signal to the DAC along with the newly calculated samples at the newly generated clock.

If you want complete software control, then the only solution right now is DIY (as I did and explained in my blog)

But this combo will cost you almost the same as a buff32...
aolsen  
#3 Posted : Wednesday, July 1, 2009 6:43:42 AM(UTC)
aolsen

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I know that CS8416 normally uses the internal PLL clock recovery however from the Product data sheet the jitter is quite high 200ps! and therefore it is better to have an external clock. Just not sure which frequency to use in order to support input signal from 32kHz to 192khz.

The ASRC (Metronome) has a clock but is not as stable as the reference clocks on the marked.

It would be the best - I assume - to have an external reference and then supply the clock to SPDIF/ASRC/DAC so that is what I'm aiming at.

Hopefully it is possible.

/ Allan

glt  
#4 Posted : Wednesday, July 1, 2009 8:06:13 AM(UTC)
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The 200 ps jitter is inherent jitter in the design. I don't think you can do anything about that figure. Get the Wolfson receiver that has 50 ps
aolsen  
#5 Posted : Thursday, July 2, 2009 1:41:37 AM(UTC)
aolsen

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Hmm - it just seems strange if the chip is independent on the jitter level on the external reference clock. I have aksed Wolfson about the external reference clock jitter sensitivity. I was just thinking garbage in => garbage out ;-). It seems like Wolfson is at least interested in reducing the jitter in the system. On their site they have published AES papers about jitter - haven't read them in details.

http://www.wolfsonmicro....0receiver_Oct%202006.pdf
http://www.wolfsonmicro....Jitter%20Performance.pdf
http://www.wolfsonmicro....er_v1.2%20May%202007.pdf

Edited by user Thursday, July 2, 2009 1:43:46 AM(UTC)  | Reason: Not specified

Brian Donegan  
#6 Posted : Thursday, July 2, 2009 5:35:01 AM(UTC)
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I think the point GLT was making is that in the setup you describe, the Metronome will be the clock master. The jitter coming from the S/PDIF module becomes almost irrelevant*, and new clock signals are generated in the ASRC.

* If the jitter were really bad, it would be important, but with either of the S/PDIF receiver modules, that's not the case.
aolsen  
#7 Posted : Friday, July 3, 2009 1:07:43 AM(UTC)
aolsen

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Thanks Brian and GLT,

I am not sure that I understand completely that jitter introduced in the SPDIF reciever will not have any impact on the sound. Can you elaborate on this? It looks like the Wolfson has better jitter figures however I need the 2 SPDIF inputs ;-( so I need to go for the CS8416.

Maybe it is the wrong forum but is there any disadvantage of making SPDIF/ASRC board based on the CS8422 or SRC4392 compared to the CS8416/WM8804+SRC4192?Think
Brian Donegan  
#8 Posted : Friday, July 3, 2009 6:32:03 AM(UTC)
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Quote:
I am not sure that I understand completely that jitter introduced in the SPDIF reciever will not have any impact on the sound. Can you elaborate on this?


Jitter is basically a variation between the data and the clock the describes the timing of that data. (The jitter numbers you are reading aren't saying that the receiver is introducing the jitter, but that it can have as much as that much jitter.) The ASRC reclocks and re-times the clock and data signals, theoretically removing (or drastically reducing) the jitter error of the input signal. This assumes that the input jitter isn't so bad that the ASRC cannot properly reconstruct the digital signal, but even with USB audio, which typically has much higher jitter numbers than we are discussing here, the ASRC can provide a very low jitter, and very accurate output.
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Reference DAC med external reference clock with digital volume control (S/PDIF Transceiver (WM8804))
by aolsen 6/30/2009 3:38:16 PM(UTC)
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