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steveww  
#1 Posted : Saturday, November 20, 2010 8:09:29 AM(UTC)
steveww

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I have a dual mono set up with Volumite controller.

On initial power up occasionally one of the Opus boards will not boot properly and the power has to be cycled again. My guess here is that the Volumite is sending the set up instructions before the Opus is ready.

What sort of delay did you program in to allow for this?

Unless you are going to issue a patched version of the firmware I guess I will have to engineer some delay in to the Volumite power line so it powers up a tad later than the Opus.
Russ White  
#2 Posted : Saturday, November 20, 2010 3:10:58 PM(UTC)
Russ White

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There is already a 50ms delay. If your DAC PS rise time is too close to 50ms then you will need to figure out some kind of power sequencing or reroute things a bit.

I have never observed what you are describing, but this probably because I always power the Volumite directly from the host to prevent this kind of thing.

What is your PS rise time? How are you powering the volumite? Have you tried powering it a different way?

One way to resolve this issue would be to power the volumite from the digital supply of DAC itself. This way both the DAC and the volumite should come up at the same time.

The volumite can work at either 5V or 3.3V.

Edited by user Saturday, November 20, 2010 3:12:25 PM(UTC)  | Reason: Not specified

steveww  
#3 Posted : Sunday, November 21, 2010 7:05:49 AM(UTC)
steveww

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I have double checked this by putting a manual switch between the Volumite and the PSU, this lets me cycle the Volumite independently of the other components in the system. Cycling the Volumite once the main power is on always clears the problem.

On the PSU side of things I have 2 Placids each powering an IVY. One LCBPS feeding the Ballsie (Balanced will be my main output). One LCDPS feeding the all the digital bits: Opus X 2, 8804, Toslink and Volumite. One side of the LCDPS feeds all the digital side and the other just does the analogue stage of the Opus. Theoretically then as all the digital bits share the same regulator they should all come up together. Alas not always. It appears to be totally random how each Opus fails to boot. Sometimes one will just fail to start, sometimes one starts in stereo mode, sometimes one starts with a different volume setting to the other, etc.

I have followed the guidelines for the I2C bus and as the run is around 10cm I am using a twisted pair of SDA/GND and SCL/GND, each twisted pair is approx 1cm from the other. The run goes from the Volumite to the first Opus then via the shortest links possible (not twisted) to the other Opus directly underneath it. Once booted up the volume control appears to track correctly so I am reasonably confident that the I2C bus is working OK.

I am going to have to build a little delay circuit to trigger a relay on the Volumite power line may be 0.5 sec after initial power up. IMHO 50ms is really not long enough for the power lines to settle across multiple modules like this. In this situation speed is not important but reliability is so 500ms would be OK to really nail it.
Russ White  
#4 Posted : Sunday, November 21, 2010 7:33:59 AM(UTC)
Russ White

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I don't doubt you you have a PS sequencing issue, and I am quite sure it can be solved.

If you look at the tri-state switch on the Opus you will see two pads on one side. One is connected to GND and one to DVCC. Solder a wire from the DVCC pad and power your volumite directly from that.

Don't use the Volumite's on-board regulator in this case.

I just tested my pair of Opus and I can't replicate your issue, but I am powering my volumite as I just described.

If you really need to a simple RC delay with a transistor should suffice in your case.

The reason you don't want a long software delay is because the default mode for the DAC is 0dbfs output, so for a small period you could get full scale noise going to a system and possibly blowing speakers etc. That is why the delay is not longer. In your case this may not matter, but in some it could mean the difference between success and a blown speaker.

Edited by user Sunday, November 21, 2010 8:03:46 AM(UTC)  | Reason: Not specified

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