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Hi, I would like to try your transciever with a tda 1543 dac, but I'm not sure about a few basic things.
Is there any particular configuration I should use? It's not clear to me from the manual.
Why is the 74ac240sc needed on the board?
How should the transciever be connected to the BCK, WS and DATA of the dac?
If all I need is the receiver, is this board an overkill?
I began reading the datasheet for the 8804 and my head started to spin. I'm not competent enough to follow what goes on with this chip.
Thanks for any help, Marco
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Rank: Member
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Groups: Administration, Customer Joined: 10/24/2006(UTC) Posts: 2,868 Location: Massachusetts, USA
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I don't really have any experience with the TDA chip, so am not in a position to offer advice.
The 74ac240sc chip is only there to handle the status LEDs, and does not interact with the digital signals at all.
For connections, BCK is BCK (Bitclock), WS is LRCK (Word select or LeftRightClock), and Data is Data. I am not sure if the TDA needs the MCK (Master Clock). You will also need a common ground for clock voltage reference.
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Just did a quick search. The TDA chip does not need MCK, so just leave that disconnected.
You will want to select 16-bit word length on the S/PDIF Transceiver (AIFCONF0 and AIFCONF1 switches set to -).
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Thank you. Other than the 16bit thing, are all those parameters that appear on the 8804 datasheet irrelevant for this application? For instance, if I buy the naked pcb and get the parts separately, do I need to program anything on the chip?
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what's the right justified option?
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Groups: Administration, Customer Joined: 10/24/2006(UTC) Posts: 2,868 Location: Massachusetts, USA
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No, the chip operated in hardware mode, and configuration is controlled by the tri-state DIP switches on the board. All the supported configuration options are detailed in the user manual.
AIF/MS switch toggles Master/Slave mode of the MCK (Master Clock). + (1) is Master Mode, - (0) is Slave Mode. TXSRC switch toggle whether the board is an S/PDIF Receiver (outputting I2S) or S/PDIF Transmitter (inputting I2S data) AIFCONF1 / AIDCONF0 Control Work length and justification (see page 19 of the datasheet)
Right-justified I2S is just a different flavor of I2S, where the data bits are right justified, rather than left-justified, in the 16- or 24-bit words. You will need to consult the Datasheet of your DAC chip to see what it requires.
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