Greetings,

My question is regarding the effects of the elastic buffer within the WM8804 and its effect on the relationship between incoming SPDIF data and outgoing I2S data. The application I have in mind requires a constant delta t between incoming and outgoing data bits for the purposes of phase measurements between the SPDIF data and a reference ADC that will be clocked by the MCLK output of the WM8804 device. I am concerned that if the elastic buffer is in line with the data stream and it is n bit wide then there could be as great as n/(Fs*64) seconds of delay introduced by the buffer. This might not be a problem if it is deterministic and can be calculated out as a constant phase error, but I could not confirm if that is a valid assumption or not. I would very much appreciate any insight on the subject.

Thank you,

Hey, at least you responded. Wolfson application engineers do not seem to return phone calls or emails. (They probably get a lot of cranks calling up from the states :) I will test it out when I get the board I ordered, thanks.