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Greetings If I depower the supply to the Crystek 80Mhz crystal can I tack on a direct clock feed into the appropriate crystal leg without causing issues? Just trying to avoid removing a four point soldered crystal if possible. http://www.crystekcrysta...heets/clock/CCHD-950.pdfLooks like if the writing of the crystal is upright and facing you, the pins go from top left clockwise around with pin 2 ground (top R) and pin 3 clock out (bottom R). (FYI, I realise the benefits of asynchronous clocking, however a learned friend has tried direct clocking with a Hiface into a different ESS chip with great results). Cheers. Edited by user Tuesday, August 2, 2011 8:59:53 PM(UTC)
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kpavey wrote:Greetings If I depower the supply to the Crystek 80Mhz crystal can I tack on a direct clock feed into the appropriate crystal leg without causing issues? Just trying to avoid removing a four point soldered crystal if possible. http://www.crystekcrysta...heets/clock/CCHD-950.pdfLooks like if the writing of the crystal is upright and facing you, the pins go from top left clockwise around with pin 2 ground (top R) and pin 3 clock out (bottom R). (FYI, I realise the benefits of asynchronous clocking, however a learned friend has tried direct clocking with a Hiface into a different ESS chip with great results). Cheers. I looked at my BII and found that Crystal's output goes to unused R17 pad, then to ES9018's XI pin. If you wouldn't like to remove BII's XO, depowering it and feeding your clock to rightside of R17 pad MIGHT work, I think.
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Thanks for your reply. When I checked continuiity on my crystal, pin 3 (bottom rhs when reading the writing on it) is ground. R17 is populated with 100k resistor. So now I'm unsure which pin is the clock output. Hmmmm. 
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Apologies for some of the bum steering earlier...
Pin 24 on the ESS chip is the Xtal in pin. As wktk smile said, R17 (RHS of this resistor when the TPA logo is at the top of the board) is connected to the Crystek clock output, which makes a convenient soldering point.
I unpowered the separate supply to the Crystek crystal, then connected up the Hiface clock output to this resistor pad using some Mil coax cable I had lying around. Note I grounded the source end of the coax but not the destination to avoid a ground loop but shield this high frequency signal.
Mental note - pinouts from the dot on the ESS chip go counter clockwise...and the Crystek pinout then would have made sense too...for the Crystek, pin 1 is bottom left, pin 2 bottom right, pin 3 is top right (Clock out)...
Anyhoo, it works and initial impressions are positive with the music having excellent drive (PRAT), the bass is very solid, and great inner detail (OK it had lots of the latter before). Well worth trying this guys!
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Congrats! 
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OK here's the install as mentioned above - hope it inspires others. Cheers. Edited by user Thursday, August 4, 2011 5:44:23 AM(UTC)
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Hi kpavey,
Great work!
BTW, what are those regulators you added?
Ciao!
Do
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Howdy these are Paul Hynes post regs. I also implemented 3 Hynes pre regs (much larger, capable of 2A each) to provide the 5.5V independently and this avoids ground plane crossing of the various supplies. The Vd pin from the post reg is lifted and supply provided to it (and ground) from the pre reg. This was not a trivial expense but I figured it was about time I had a reconfigurable robust digital supply for DAC projects. Edited by user Thursday, August 4, 2011 5:54:59 PM(UTC)
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kpavey: inspiring indeed. I have always wondered what the ESS 9018 might be like without the ASRC and running on the masterclock of the source. Are any changes in chip configuration necessary to do this, and are you controlling the chip over i2c?
I am about to add an I2S source to my B-II, and I might like to try this approach.
Also, what interface are you using, the evo?
I would love to hear any more details you might care to share which pertain only to running in synchronous mode.
Thanks!
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>barrows
That depends on masterclock frequency and samplerates of the recordings.
If the master clock wasn't fast enough, you might need bypassing OSF -It requires changing chip configuration-
when playing higer samplerate ones (typically 192k or higher?)
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You would not want to turn of the OSF unless your data is synchronously re-sampled. Otherwise the result would be very undesirable. The best thing to do if you desired a synchronous clock is simply to supply one that is an exact multiple of the incoming bit clock. But if you do both 44.1khz and 48khz based multiples that is going to mean two master clocks. The way to do this is to use the same master clock that is actually used to generate the bit clock (by division). I have implemented this using my XMOS proto board. It works quite well, but you still want a fairly high speed clock. Operating like this allows the DPLL to basically free wheel. It does not even have to try to maintain a lock. :) I will detail later how to do this with our USB module later. Edited by user Wednesday, August 10, 2011 11:44:53 AM(UTC)
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Just saw these reponses. Thanks Russ. I am assuming this means that the onboard oscillators in the new async USB interface are going to be very, very good, with dedicated supplies to match. All great news.
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