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Hi Russ and Brian,
I am one of of the lucky person who succeeded in placing an order in the first batch of the new Buffalo-II. Congratulations for this design, it looks very promising for the diy community.
My question is regarding the possibility of connecting a Left Justified PCM signal to the board. The ES9018 (Sabre32) chip supports this format but it must be configured in a register (it was register 10 in the ES9008). The default configuration of the ES9018, I assume, is the same as the ES9008 which is standard I2S PCM. I also intend to use Volumite with the Buffalo-II.
If my assumptions are correct, it would be a matter of making a special version of the Volumite to incorporate a command to the register responsible for the input format. Is that correct? If so, would it possible to get such a special version?
Also, does the Buff-II have a means to disable the on-board clock and a pad to inject an external clock signal, as in the first Buffalo version?
My intention is to connect the Buff-II to a Squeezebox 3 (SB3) in PCM mode and use the Buff-II clock to drive the SB3. The Buff-II would be fed with an external 45.1584 MHz clock which would be divided by 4 to connect to the SB3 master clock pad. The 45.1584 MHz clock would be divided by 4 prior to connecting it to the SB3 master clock pad since the SB3 works with a 11.2896 MHz master clock rate. This way the connection between the SB3 and the Buff-II is totally synchronous and the Buff-II acts as the master. This is a well known configuration that has been very successfully demonstrated by John Swenson in 2006.
The problem is that the SB3 doesn't internally use the standard I2S but a Left Justified format.
I know that I could use the Metronome between the SB3 and the Buff-II to convert the Left Justified format to I2S, and use the 45.1584 MHz clock divided by 2 to feed the Metronome master clock, hence still retaining the synchronous configuration, but a direct connection between the SB3 and Buff-II would be much simpler.
Thanks - Michael
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Rank: Administration
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MichaelB wrote:Hi Russ and Brian,
I am one of of the lucky person who succeeded in placing an order in the first batch of the new Buffalo-II. Congratulations for this design, it looks very promising for the diy community.
My question is regarding the possibility of connecting a Left Justified PCM signal to the board. The ES9018 (Sabre32) chip supports this format but it must be configured in a register (it was register 10 in the ES9008). The default configuration of the ES9018, I assume, is the same as the ES9008 which is standard I2S PCM. I also intend to use Volumite with the Buffalo-II.
If my assumptions are correct, it would be a matter of making a special version of the Volumite to incorporate a command to the register responsible for the input format. Is that correct? If so, would it possible to get such a special version?
Also, does the Buff-II have a means to disable the on-board clock and a pad to inject an external clock signal, as in the first Buffalo version?
My intention is to connect the Buff-II to a Squeezebox 3 (SB3) in PCM mode and use the Buff-II clock to drive the SB3. The Buff-II would be fed with an external 45.1584 MHz clock which would be divided by 4 to connect to the SB3 master clock pad. The 45.1584 MHz clock would be divided by 4 prior to connecting it to the SB3 master clock pad since the SB3 works with a 11.2896 MHz master clock rate. This way the connection between the SB3 and the Buff-II is totally synchronous and the Buff-II acts as the master. This is a well known configuration that has been very successfully demonstrated by John Swenson in 2006.
The problem is that the SB3 doesn't internally use the standard I2S but a Left Justified format.
I know that I could use the Metronome between the SB3 and the Buff-II to convert the Left Justified format to I2S, and use the 45.1584 MHz clock divided by 2 to feed the Metronome master clock, hence still retaining the synchronous configuration, but a direct connection between the SB3 and Buff-II would be much simpler.
Thanks - Michael
It would be very easy to set LJ mode. I will see what I can do for you. :) Now that said. I would absolutely not use an external clock. Because the jitter reduction works best with a frequency that is not an exact multiple of the serial clock. :) Also it needs to have extremely low phase noise and extremely short leads. The Buf-II clock is ideal. There is no way your going to get great results from on external clock. In any case you would have to remove the on-board clock as it does not have an enable pin. Once again. The clock we use is incredibly good, and you would be hard pressed to do better (not bloody likely). Now please let me explain something, the only way to run synchronous with the ES9018 is to disable the jitter correction. The ES9018 is designed specifically to be asynchronous. Running it synchronously is very very very bad thing to do because you have just sacrificed the key benefit of the DAC. :) Keep the 80mhz and just run in the PCM. Only after you have listened to that configuration should even consider anything else. I think that thought will pass quickly. :) I have run this chip configured every way you can think of. Please believe me when I say you do not want to disable jitter correction. It along with the stellar output section this is what really makes this DAC better than the rest. To eliminate the jitter correction is to put it on the level of far inferior chips. Cheers! Russ Edited by user Friday, February 19, 2010 7:18:19 PM(UTC)
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Rank: Member
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Location: Montreal, Canada
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Hi Russ, Thanks for the reply and the insight provided regarding the Buff-II/Sabre intrinsic ability to reduce jitter. I believe that as a first step I will follow your advice. Now the principle of going synchronous, and the Master/Slave relationship between the Transport and DAC where the latter is the master i.e. holding the master clock, is generally recognized as being the best approach to reduce jitter at the DAC . I know that the Sabre DAC has a genuine and unique approach regarding jitter reduction, however some are still using a synchronous method with this chip. Among them Gordon Rankin of Wavelength Audio, the well respected designer of the Denominator DAC: http://www.usbdacs.com/Products/Products.html This DAC even uses 2 master clock frequencies, one for the 44.1 khz and one for the 48 khz sampling rates base frequencies. I believe that Gordon must have found something 'different' between the async. and sync. modes overall results. Nevertheless I will begin by using the Buff-II in its native async. mode as you suggest. I appreciate your opening regarding the special version of Volumite to incorporate the Left Justified mode. Obviously I would pay the premium for this feature. Best regards, Michael
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Rank: Member
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Joined: 5/5/2010(UTC)
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Hi,
Has a custom firmware for Left Justified mode is available?
Or the only way to get Left Justified signal into the Buffalo II is using the Metronome?
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Rank: Advanced Member
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Joined: 5/4/2011(UTC)
Posts: 34
Location: Southbury, CT, USA
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Correct me if I am wrong, these are the ways I can hook up the Squeezebox 3 (SB3) to the Buffalo II: 1) SPDIF of SB3 to SPDIF of BII - Obvious 2) I2s of SB3 to I2s of BII (Method 1) - Asynch mode on BII To get I2s from the SB3, I provide an external 11.2896M clock to the SB3, re-clock the I2s signals from the SB3 using the 11.289M clock. The re-clocked I2s signals are fed to the BII. This was done by John Swenson for another dac. Now : a) I can do the Left justified to I2s externally b) I can do the Left justified to I2s in the BII 3) I2s of SB3 to I2s of BII (Method 2) - Asynch mode on BII Could I not connect the Left justified Word Clock, Bit Clock and Data signals from the SB3, without re-clocking and feed in into the BII programmed for left justified data, since it (BII) has an ASRC? Obvious issue being signal integrity(SI). 4) I2s of SB3 to I2s of BII - Synchronous mode Do what MichaelB suggested : Quote:My intention is to connect the Buff-II to a Squeezebox 3 (SB3) in PCM mode and use the Buff-II clock to drive the SB3. The Buff-II would be fed with an external 45.1584 MHz clock which would be divided by 4 to connect to the SB3 master clock pad. The 45.1584 MHz clock would be divided by 4 prior to connecting it to the SB3 master clock pad since the SB3 works with a 11.2896 MHz master clock rate. This way the connection between the SB3 and the Buff-II is totally synchronous and the Buff-II acts as the master. This is a well known configuration that has been very successfully demonstrated by John Swenson in 2006. Again the left justified is either done outside or inside. Is the BII internal clock available to tap for the newer boards? Thanks Simmonds
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